HCLTech analog layout hiring 2026 for VLSI freshers in Hubli
The HCLTech analog layout opening in Hubli is meant for freshers who have already done formal training or an internship in VLSI analog layout design. If you have only studied layout in class, this is not your role yet. If you have finished a layout course or a lab internship, read on.
The job sits on HCLTech's Campus-Beginner track, the company's label for campus and fresher hiring. The title on the page is Designer, Analog Layout Design. You will work under experienced layout engineers on analog, mixed-signal and custom layout blocks for real customer projects. HCLTech's careers system lists this posting until 31 December 2026; the job page itself shows no last date.
Training or internship comes first
The listing is direct about the entry bar. It wants candidates "who have completed formal training or internship programs in VLSI Analog Layout Design." That one line does most of the filtering.
The page also says HCLTech's own training stresses CMOS basics, IC fabrication, Cadence-based analog layout and project-led learning. So the company expects you to arrive with layout basics, and then it builds on them. It does not ask for a work history in years, and it names no batch or minimum score.
In practice, a good fit for this HCLTech analog layout role has at least one of these, all drawn from the skills the listing prefers:
- a finished analog layout course with lab work on a real tool;
- an internship where you placed and routed analog or mixed-signal blocks;
- a training project in custom layout that you can show and explain.
Blocks you would help lay out
The main duty is to support custom layouts for analog and mixed-signal circuits. The listing names the blocks you would work on:
- amplifiers
- current mirrors
- comparators
- LDOs, or low drop-out regulators
- bandgap circuits
- level shifters
- oscillators
- DACs and other analog sub-blocks
Next comes floorplanning and routing. You support floorplans built around design limits, then place devices and route them under a senior's eye. The listing says you will learn routing for analog signal integrity, shielding and power distribution. It also mentions area use and layout quality. The page notes that junior layout engineers have handled op-amps, current mirrors, level shifters, LDOs and amplifiers early in their careers.
You will also join technical reviews, training sessions and team discussions with layout engineers, circuit designers and leads. The listing asks you to keep to quality and schedule commitments on each project.
Verification work and tools
Physical verification is a set duty. You run basic checks and fix the errors with help from senior engineers. The listing names four checks:
- DRC, the design rule check
- LVS, layout versus schematic
- antenna checks
- density checks
You are also expected to learn what sign-off needs and how layout quality is judged. For tools, the HCLTech analog layout listing wants academic, internship or training exposure to one or more of these: Cadence Virtuoso, Calibre, Assura, PVS and other layout verification tools. Basic scripting is a plus. The page names SKILL and Shell as part of HCLTech's own training.
Degrees HCLTech accepts
The education line is exact. A B.E. or B.Tech in one of these branches qualifies:
- Electronics and Communication Engineering
- Electrical and Electronics Engineering
- Electronics Engineering
- Instrumentation Engineering
So does an M.Tech or M.E. in VLSI Design, Microelectronics, Semiconductor Technology or Embedded Systems. Computer science is not on the list. BCA, B.Sc and MCA are not named either, so this is an engineering-only opening. For wider options, see the jobs for engineering graduates or the MCA and M.Sc openings on Classic Jobs.
Layout skills to sharpen now
The must-have skills are fundamentals, not tool tricks. Plan your revision around what the listing names. The study points below are general layout knowledge, matched to each line of the listing.
Start with CMOS devices and electronic circuits. Be able to explain how a current mirror copies a current, and why two matched transistors in a differential pair should sit close together. Then cover semiconductor fabrication at a basic level, since layout rules come from what the fab can build.
Next, the layout ideas the listing names directly: matching, symmetry, shielding and guard rings. It also lists common-centroid structures as a practice to learn. Draw a common-centroid pair of transistors and explain why it reduces mismatch. If you can sketch one on paper and justify each choice, you are covering a skill the listing names.
Finally, the tool side. If you trained on Cadence Virtuoso, be ready to describe a block you laid out, the DRC and LVS errors you hit, and how you fixed them. If your training used another tool, say which one and what you built. The HCLTech analog layout listing accepts exposure to "one or more" tools, so you do not need all of them.
Analog layout doubts, answered
Can I apply without an internship?
Yes, if you have finished formal training in VLSI analog layout. The listing asks for training or an internship, not both.
Is this role open to CSE graduates?
The listed branches are ECE, EEE, Electronics and Instrumentation for B.E. or B.Tech, plus four M.Tech or M.E. streams. CSE is not named.
What is the salary?
The listing does not state pay.
Is there a last date?
The job page shows none. HCLTech's careers system lists the posting until 31 December 2026.
Apply on the company's own page: HCLTech analog layout listing (149813). The listing mentions no fee, and you should not have to pay anyone to apply or to get an interview.
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